Please use this identifier to cite or link to this item:
http://dspace.hebron.edu:8080/xmlui/handle/123456789/142Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hasasneh, Nabil | - |
| dc.contributor.author | Bell, Ian | - |
| dc.contributor.author | Jesshope, Chris | - |
| dc.date.accessioned | 2019-08-07T14:40:58Z | - |
| dc.date.available | 2019-08-07T14:40:58Z | - |
| dc.date.issued | 2007-01-01 | - |
| dc.identifier.uri | http://dspace.hebron.edu:80/xmlui/handle/123456789/142 | - |
| dc.description.sponsorship | This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token to the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring’s timing. The arbiter provides a very simple arbitration mechanism and can be used for chip multiprocessor arbitration purposes. | en_US |
| dc.publisher | Journal of Systems Architecture | en_US |
| dc.relation.ispartofseries | 5-6;253-262 | - |
| dc.subject | multiprocessors | en_US |
| dc.subject | chip | en_US |
| dc.title | Asynchronous arbiter for micro-threaded chip multiprocessors | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Journals | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Asynchronous arbiter for micro.pdf | 90.17 kB | Adobe PDF | View/Open |
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