Please use this identifier to cite or link to this item: http://dspace.hebron.edu:80/xmlui/handle/123456789/137
Title: Instruction level parallelism through microthreading—a scalable approach to chip multiprocessors
Authors: Hasasneh, Nabil
Bousias, Kostas
Jesshope, Chris
Keywords: parallelism
multiprocessors
microthreading
chip
Issue Date: 1-Feb-2006
Publisher: The Computer Journal
Series/Report no.: OUP;
Abstract: Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction level parallelism (ILP). The most significant problem with this approach is a large instruction window and the logic to support instruction issue from it. This includes generating wake-up signals to waiting instructions and a selection mechanism for issuing them. Wide-issue width also requires a large multi-ported register file, so that each instruction can read and write its operands simultaneously. Neither structure scales well with issue width leading to poor performance relative to the gates used. Furthermore, to obtain this ILP, the execution of instructions must proceed speculatively. An alternative, which avoids this complexity in instruction issue and eliminates speculative execution, is the microthreaded model. This model fragments …
URI: http://dspace.hebron.edu:80/xmlui/handle/123456789/137
Appears in Collections:Journals

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