This paper introduces a case study of the E-learning experience at Hebron University (HU). Over the last few years, we have been building up a set of case studies illustrating different ways in which learning technologies ...

Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction level parallelism (ILP). The most significant ...

This paper presents a scalable and partitionable asynchrono-us bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a ...

Chip multiprocessors (CMPs) hold great promise for achieving scalability in future systems. Microthreaded CMPs add a means of exploiting legacy code in such systems. Using this model, compilers generate parametric concurrency ...