Please use this identifier to cite or link to this item:
Title: Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors
Authors: Hasasneh, Nabil
Bell, Ian
Jesshope, Chris
Keywords: multiprocessors
Issue Date: 1-Jan-2006
Publisher: International Conference on Architecture of Computing Systems - Springer, Berlin, Heidelberg
Series/Report no.: ;252-267
Abstract: This paper presents a scalable and partitionable asynchrono-us bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring’s timing. It is shown that this arbiter can be extended easily to support large numbers of processors and can be used for chip multiprocessor arbitration purposes.
Appears in Collections:Journals

Files in This Item:
File Description SizeFormat kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.